Author Topic: [SOLVED] SPI problems  (Read 611 times)


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Re: SPI problems
« on: August 04, 2016, 05:22:37 am »
I just tried your suggestion mr mc-Abe, but no difference. Tried modus 0 till 4 I can see differences in the polarity of the clock, also switched the MOSI with the CLK line on my logic analyser. But after studying some examples on the internet and making a working example on the SPI on my Feather Huzzah, I can only conclude that the signal is totally off. The only resembling with a correct pattern is that clock is symmetric and the CS line is working but than in my example and on the internet I see mostly bursts of the clock-signal for each byte, and also the typical pattern transmitting the bytes 0, 1, 2, 3, 4 I did in both test are totally off. I give you the working test on my Feather Huzzah in attachment. You can see clearly how the information is correctly interpreted by the analyser and how the clock and Mosi line behaves in time.

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